1. Field of the Invention
The invention relates to techniques for modeling the performance of electrical circuits. More specifically, the invention relates to a method and an apparatus that uses a cell-level model to characterize and analyze the propagation of noise through an integrated circuit.
2. Related Art
Advances in semiconductor fabrication technology continue to decrease the minimum feature size that is attainable on an integrated circuit. This allows larger amounts of circuitry to be incorporated onto a single semiconductor die. At the same time, increasing clock speeds are causing this circuitry to switch at increasingly faster rates. Both of these factors are increasing the significance of noise caused by capacitive coupling between adjacent signal lines, and by inductive effects on long signal lines. Moreover, decreasing power supply voltages dictate lower transistor threshold voltages, and therefore smaller noise margins, which causes a significantly reduced signal-to-noise ratio for both digital circuits and mixed analog/digital circuits.
The above-described factors can cause “noise glitches” to be induced in signals lines within integrated circuits. These noise glitches can cause timing degradation in switching nodes, or can cause false transitions in steady-state “quiet” nodes. These false transitions can propagate through the circuit, and can cause functional errors or failures.
It is important to be able to accurately detect these noise-induced errors before a semiconductor chip is fabricated. Otherwise, a chip may not function properly, and it may be necessary to perform a “mask re-spin,” which can cost hundreds of thousands (or possibly millions) of dollars and can significantly delay the release of a product.
Circuit designers typically use timing simulators that operate on a computer-based model of a circuit to simulate the timing of the circuit. The results of these timing simulations are used to verify that the circuit meets timing requirements, and if not, to adjust the design of the circuit. Unfortunately, these timing simulations are presently unable to accurately simulate “noise glitches” over a large number of circuit elements.
General-purpose circuit simulators, such as SPICE™, can be used to accurately model noise glitches. However, such general-purpose circuit simulators are computationally intensive, and consequently require a significant amount of time to model noise on a small number of circuit elements. This makes it impractical to simulate the effects of noise on larger circuits.
Hence, what is needed is a method and an apparatus for accurately and efficiently modeling the effects of electrical noise on larger circuits.